基于FPGA CPU数据通路的设计与实现

The Design-implementation of Embedded CPU data path Based on FPGA

针对MIPS CPU流水线工作过程产生的数据相关,基于FPGA设计并实现了能有效解决数据相关的数据通路。设计五种基本数据通路,并采用流水线技术将它们整合成五级数据通路;在EX段后到ALU之间和WB段后到ALU之间构建旁路通路,从而形成总的数据通路;使用VHDL实现数据通路;编写测试程序对数据通路进行验证,并在FPGA平台上进行仿真验证。结果表明:所设计的数据通路能使数据正常流动,解决由数据相关产生的断流问题。

Aim at the data hazard which happens in the MIPS CPU pipeline, a data path was designed and implemented on FPGA, and the data path can resolve data hazard. First five basic data path was design, and the five basic data path were converted into five stage data path with pipeline technology; Forward path was constructed between EX and WB to ALU, then the whole data path came into being; The design of data path was implemented with VHDL; The test program was wrote for testing data path, and the data path was verified at FPGA hardware terrace. The result shows that the data path makes each stage work normally and resolves the break because of data hazard.