基于VHDL的数字倍频器设计

Design of Digital Frequency Multiplier Based on VHDL

介绍了数字倍频电路的工作原理,分析了倍频器产生误差的原因,然后给出用VHDL语言来实现数字倍频器的方法,并用Max+plusⅡ通过仿真进行了验证。

Introduced digital frequency multiplier of circuits operating principle, an analysis of frequency multiplier have a reason for the error, and then gives by VHDL language to realize digital frequency multiplier method, and Max ＋ plus Ⅱ verifies through the simulation.