全数字接收机定时恢复算法的FPGA实现

Implement of timing recover algorithm in all-digital receive

提出了一种基于FPGA的全数字接收机定时恢复的实现方法,分析了系统每个模块的作用,给出每个模块的硬件实现方法。最后在Quartus Ⅱ7.0编写Verilog HDL代码和测试激励,并用ModelSim对定时恢复算法进行仿真验证,结果表明,这种算法时钟抖动小,定时精度高。

This paper presents a method based on FPGA for implementing timing recover algorithm in all-digital receiver. Firstly, it analyzes each module in the system, then, proposes a hardware implementation method. Finally, the relative Verilog HDL codes and testbench are developed in Quartus 117.0 and simulated in ModelSim. Result shows this algorithm has low clock jitter and high quality.