基于FPGA的高精度时间数字转换电路设计

The Design of High Resolution Time to Digit Converter Based on FPGA

本文介绍一种基于FPGA高精度时间数字转换电路的设计方法,利用片内锁相环(PLL)和环形移位寄存器,采用不高的系统时钟便可得到很高的时间分辨率,且占用较少逻辑资源。可作为功能电路独立使用,也可作为IP核方便地移植到其他片上系统(SOC)中。在Altera公司的Stratix和Cyclone系列芯片上实现时,时间分辨率最高可达3.3ns。时序仿真和硬件测试表明该方法的可行性和准确性。

The paper introduces a new design method of Time-to-Digital Converter with high precision, which invokes the PLL and Ring Shift Register in the chip. The circuit applying the design method has been implemented in FPGA/CPLD （Field Programmable Gate Array or Complex Programmable Logic Device） ,and it could be used as the functional circuit dependently or implanted into other SOC （System on Chip） designs conveniently. The precision with 3.3 nanoseconds can be achieved in Stratix and Cyclone series chip produced by Ahera. Timing simulation and testing data indicate the method is right and feasible.