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OpenSPARC T1处理器Cache机制研究及优化 被引量:1

Study and Optimization on Cache Mechanism of OpenSPARC T1 Processor
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摘要 在现代微处理器的设计中,Cache是整个处理器性能的决定因素。本文描述了64位RISC微处理器"OpenSPARC T1"中的Cache的功能和结构,并提出对"OpenSPARC T1"中的Cache的优化方案。 In modern designing of microprocessor, Cache is the decisive factor to performance of the hole processor. In this thesis we describe the function and structure of Cache in "OpenSPARC Tl",which is 64 bits in RISC architecture, we also propose a method to optimize the performance of Cache in "OpenSPARC TI".
作者 胡小龙 杨蕊
出处 《微计算机信息》 2009年第2期267-268,271,共3页 Control & Automation
关键词 高速缓存 仿真 缺失率 Cache Simulation Miss rate
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参考文献5

  • 1OpenSPARC TI Microarchitecture Specification.
  • 2王熹微,唐昆,崔慧娟.基于DM642的视频编码Cache优化策略[J].微计算机信息,2005,21(09Z):84-86. 被引量:21
  • 3A. Malik, B. Moyer, D. Cermak, "A Low Power Unified Cache Architecture Providing Power and Performance Flexibility," Int. Symp. on Low Power Electronics and Design, June 2000.
  • 4Austin T, Ernst D,Larson E,et al.Simplescalar Tutorial v4.0.
  • 5Glen Reinman and N.P. Jouppi. “CACTI2.0: An Integrated Cache Timing and Power Model,” 1999. COMPAQ Western Research Lab.

二级参考文献3

  • 1TMS320DM642 Video/Imaging Fixed—Point Digital Signal Processor Data Manual.Texas Instruments,sprs200B,May 2003.
  • 2TMS320C6000 DSP Cache User's Guide.Texas Instruments,spru656A,May 2003.
  • 3Cache Analysis User’s Guide.Texas Instruments,spru575A,January 2003.

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