差分LC压控振荡器相位噪声和功耗的优化

Phase Noise and Power Optimization of a 2-GHz Differential CMOS LC VCO

基于0.18um射频CMOS工艺,提出三种LC压控振荡器相位噪声和功耗的优化方法。主要思想是:一,通过精心设计,使得PMOS和NMOS差分晶体管对的跨导相等,从而取得对称的输出电压;二,采用偏置晶体管的噪声滤除技术,进一步降低相位噪声;三,确保差分晶体管对的工作区域始终在饱和区和三极管区的边界上,从而实现相位噪声和功耗的最优化。仿真结果证明,在中心频率为2GHz、频率调谐范围为12.4%的条件下,得到最优化的相位噪声为:-102.6dBc/Hz@100KHz、-121.1dBc/Hz@600KHz,且功耗仅为5.4mW。

The phase noise and power optimization of a 2-GHz differential LC VCO by CMOS 0.18-um RF IP6M technology is presented. The key ideas to achieve phase noise optimization are delicate designs of a symmetric circuit and a technology to filter out the top-biased transistor＇s noise. Moreover, In order to obtain good phase noise performance with low power consumption, the oscil- lation output amplitudes are well designed to ensure the differential pair transistors operate at the boundary between saturation and triode. The phase noise is -102.6dBc/Hz at 100 KHz and -121.1dBc/Hz at 600 KHz offset frequencies with a 12.4% tuning range for a 5.4mW power consumption.