用VHDL实现的23位快速浮点数加减法器

The realization of the fast adder-subtracter for the 23 bit’s floating point numbers by VHDL

随着大规模集成电路的不断发展,FPGA/CPLD在数字信号处理、自动控制等方面得到了越来越多的应用。并且伴随着数字化处理技术的不断发展,为满足系统功能的要求,对浮点数运算的速度以及相应占用的资源也就提出了更高的要求。笔者即介绍了以VHDL语言为基础,采用并行算法且计算速度达到33MHz的,对23位标准浮点数实现的高速浮点加减法运算器,并以Cyclone II芯片EP2C20F484为硬件环境,最终进行时序模拟仿真,从而验证该浮点加减法器的正确性和快速特性。

With the development of LSI, FPGA/CPLD has been used more and more in the fields of digital signal processing and auto-control amt so o71. And with the development of the techniques of digital processing, for fitting the system＇s function, it should be a higher requirement to speed and used-resource to compute the floating point numbers. The author introduces a high speed adder-subtracter of the 23 bit＇s floating point numbers, which is carried out with the parallel arithmetic and the computational speed could be up to 33M Hz by the VHDL. And take the EP2C20F484 which is a kind of Cyclone II as the hardware environment to getting the timing emulate, which could prove its correct and fast character.