一种低噪声高频合成时钟源的设计和实现

Design and Realization of a High Frequency Low Noise Clock Synthesizer

本文介绍了PLL合成时钟源的原理,介绍了MC12429的结构,设计出了高频时钟源电路图。测试结果表明本设计的输出信号质量好。该信号源结构简单,广泛用于通信、仪器仪表、自动控制等领域。

The paper introduces the principle of PLL clock synthesizer and the structure of MC12429,designs the circuit of the High Frequency Clock Synthesizer .The test result indicates that the output signals of this design have the excellence performance. The design has simple structure, and can be used in communication ,equipment and meter, auto control extensively.