期刊文献+

一种低电源电压的CMOS四象限模拟乘法器

A Low Power-Supplies' CMOS Four-Quadrant Analog Multiplier
原文传递
导出
摘要 介绍了一种工作在低电源电压下的CMOS四象限模拟乘法器.为保证在较低的电源电压下有较大的线性电压输入范围和较小的非线性失真,电路采用了特殊的设计.SPICE的模拟结果表明,在±2.5V电源电压下,线性输入范围大于±1.5V,在此范围内该电路的总谐波失真小于0.8%,-3dB带宽分别大于3.0MHz和8.5MHz,功耗小于1.4mW.特别当电源电压降低至±1.5V时电路仍可正常工作,具有大于±0.5V的线性输入范围和小于0.4%的总谐波失真,表明该电路完全适用于低电压供电系统. A CMOS four-quadrant analog multiplier operable on low power-supplies is presented. In order to keep wide full-scale linear input range and low nonlinearity error on low power-supplies,the multiplier is designed using special technique. The SPICE simulation results are given. The circuit is biased with ± 2. 5 V supplies and power consumption is below to 1. 4 mW, and the full-scale linear input range is more than ±1. 5 V. The total harmonic distortion is less than 0. 8 percent and the nonlinearity error is less than 1. 1 percent over ±1. 5 V input range, the -3 dB bandwidth is 3. 0 MHz and 8. 5 MHz. Especially, when power-supplies is below to ±1. 5 V, the circuit can operate well, with a full-scale linear input range of ±0. 5 V and a total harmonic distortion less than 0. 4 percent. The proposed circuit is proved to suit for low power-supplies' systems.
出处 《复旦学报(自然科学版)》 CAS CSCD 北大核心 1998年第1期74-80,共7页 Journal of Fudan University:Natural Science
基金 国家自然科学基金
关键词 低电源电压 模拟乘法器 CMOS 集成电路 设计 low power-supplies analog multiplier
  • 相关文献

参考文献3

  • 1Liu Sheniuan,IEEE Trans Circuits Syst I,1995年,42卷,2期,119页
  • 2李联,MOS运算放大器.原理、设计与应用,1988年
  • 3Qin Shicai,IEEE J Solid-State Circuits,1987年,22卷,6期,1143页

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部