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IEEE1394总线容错性研究 被引量:1

On Fault-tolerance of IEEE1394 PHY/Link Interface
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摘要 IEEE1394总线正逐步应用于航天电子系统,因此对其容错性进行研究是非常必要的.本文对IEEE1394总线的物理层与链路层接口部分在信号传输中可能存在的错误以及如何容错进行了研究,重点分析了物理层控制双向总线时可能出现的各种错误,并给出了链路层的容错方法,这样可以在很大程度上提高网络系统运行的可靠性. IEEE1394 bus is a high performance commercial bus standard. Today, it is gradually used in avionics. So it is necessary to study the fault tolerance of IEEE1394 to meet the avionics reliability and performance requirements. In this paper, the study is focused on the fault tolerance of PHY/link interface. All kinds of fault possibly presented in the interface signals between physical layer and link layer under PHY control, were analyzed. The techniques of how to avoid these faults for serious damage to avionics were provided.
出处 《空间科学学报》 CAS CSCD 北大核心 2009年第1期107-111,共5页 Chinese Journal of Space Science
关键词 IEEE1394 物理层 链路层 容错 IEEE1394, PHY, Link layer, Fault tolerance
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参考文献4

  • 1Tai A T et al. COTS-based fault tolerance in deep space: qualitative and quantitative analyses of a bus network architecture. In: Proceedings of the 4th IEEE International Symposium on High Assurance System Engineering, 1999. 97-104
  • 2Chau S N, Alkalai L, Burt J B, Tai A T. The design of a fault-tolerant COTS-based bus architecture. In: Proceedings of 1999 Pacific Rim International Symposium on Dependable Computing (PRDC'99), 19,99
  • 3IEEE1394, Standard for a High Performance Serial Bus. Institute of Electrical and Electronic Engineers, 1995
  • 4IEEE1394A, Standard for a High Performance Serial Bus (Supplement), Draft 2.0. Institute of Electrical and Electronic Engineers, 1998

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