自动映射多循环程序到有限FPGA资源的参数化流水线模板

Pipelined Template for Mapping Multiple Loop Nests on FPGA with Restricted Resources

FPGA为加速计算密集型应用提供了一个灵活高效的平台.然而,由于片上资源有限,在一些情况下,需要将大规模应用中包括的多个循环程序分别映射到FPGA上执行,当一个循环程序执行完毕后,需要重新配置FPGA以执行下一个循环程序,FPGA重构过程在整个程序执行过程中占用了较多时间.文中设计了一个参数化流水线模板,并提出了相应的指令分配调度策略,实现了自动将多循环程序顺序映射到目标FPGA片上系统,同时在程序切换时,不需要进行FPGA重构.实验结果表明,对每个循环程序,文中设计的流水线模板能达到与专用硬件结构相当的执行节拍,同时节约了程序切换时的重构时间.

FPGA provides a convenient and flexible solution to speed up loop-intensive algorithms. However, these loop nests in a large scale application have to be mapped onto the target FPGA orderly because of the limited resources on-chip. FPGA reconfiguration which needs a long time is inevitable when switching between the loop nests. This paper presents a pipelined template and instruction schedule method corresponding to execute all the loop nests in sequence without FPGA reconfiguration. Experiments show that the pipelined template can achieve a comparative execution cycles for a loop comparing with the special hardware and without the need of FPGA reconfiguration.