嵌入式网卡芯片设计及其低功耗DFT技术考虑

An Ethernet Controller SoC Design and Its Low-Power DFT Considerations

针对目前应用于信息家电的以太网多芯片解决方案具有成本高、性能较低等问题,文章设计实现了一款以太网控制SoC单芯片。同时,为了获得较低的测试功耗,进行了可测试技术的低功耗优化。该芯片采用TSMC 0.25μm2P4M CMOS工艺流片,裸片面积为4.8×4.6 mm2,测试结果表明,该嵌入式以太网控制SoC芯片的故障覆盖率可达到97%,样片的以太网数据包最高吞吐量可以达到7 Mbits/s。

In this paper, an Ethernet controller SoC solution and its low power DFT for information appliances are presented. On a single chip, an enhanced one-cycle 8-bit MCU, MAC circuit and embedded memories such as SRAM, ROM and flash are all integrated together. In order to achieve high fault coverage, at the same time with low test power, different DFT techniques are adopted for different circuits： the scan circuit that reduces switching activity is implemented for digital logic IP; BIST-based method is employed for the on-chip SRAM and ROM. The SoC chip is implemented suc- cessfully by using TSMC 0.25 μm two-poly four-metal mixed signal CMOS technology, the die area is 4.8 ×4.6 mm^2. Test results show that the maximum throughput of Ethernet packets may reach 7 Mbps.