期刊文献+

GPS校频系统的优化带宽设计 被引量:2

Optimal bandwidth design for low noise GPS frequency calibration system
下载PDF
导出
摘要 精密时间频率在现代社会有着重要的作用。本文设计了一种将远距离传输GPS标准秒脉冲信号的优良长稳性能与可调本地频率源的优良短稳性能结合起来的锁相系统,得到了高稳定度、高精度的时间频率标准源。论文对GPS校频系统进行了合理简化,建立起易于分析的数学模型,然后对校频系统中关键的难点——噪声抑制问题进行了重点分析,进而设计了系统的优化带宽,并进行了仿真和实验验证。结果表明了优化带宽设计的合理性,满足了GPS校频系统的精度要求。 precise time and frequency are crucial in many application fields of industry, traffic,telegraphy and military affairs. In this paper, a high stability and precision frequency source is developed using a PLL framework, which synthesizes the excellent characteristic of long term stability of a standard 1PPS transmitted from a long distance with the excellent characteristic of short term stability of a local frequency source. The actual GPS frequency calibration system is properly simplified to make it easier to analyze, then a frequency calibration mathematic model is established based on above analysis. After a detail analysis on the key problem of GPS frequency calibration system-noise suppression, an optimal bandwidth is designed in order to achieve very low noise. Simulation and experiments were carried out; final results prove that the proposed optimal bandwidth design is proper, which meets the requirement of high precision frequency cali- bration system.
出处 《电子测量与仪器学报》 CSCD 2009年第1期32-36,共5页 Journal of Electronic Measurement and Instrumentation
关键词 标准秒脉冲 恒温晶振 GPS IPPS OCXO GPS.
  • 相关文献

参考文献8

  • 1LIM K, PARK C H, KIM D S, et al. A low-noise phase-locked loop design by loop bandwidth optimization[J]. IEEE Journal of Solid-State Circuits, 2000, 3 (6) : 807-814.
  • 2CHOIYS, HOIHH,KWONTH. Anadaptive bandwidth phase locked loop with locking status indicator [J]. Radiotechni cs, Electronics, Communications, 2005,3:826-829.
  • 3VENCESLAV KROUPA F. Noise properties of PLL systems[J]. IEEE tran. on Communications, 1982,30 (10) : 2244-2252.
  • 4VAMVAKOS S D, WERNER C, NIKOLIC B. Phaselocked loop architecture for adaptive jitter optimization [C]. IEEE ISCAS2004,2004,25 (4) :161-164.
  • 5LAI X L, WAN Y Y, ROYCHOWDHURY J. Fast PLL simulation using nonlinear VCO macromodels for accurate prediction of jitter and cycle-slipping due to loop non-idealities and supply noise[J]. in ASP-DAC 2005,8:459-464.
  • 6HINZ M, KONENKAMP I, HORNEBER E H. Behavioral modeling and simulation of phase-locked loops for RF front ends[J]. IEEE Midwest Symp. on Circuits and Systems. 2000:194-197.
  • 7NONIS R, DALT D N, PALESTRI P, et al. Modeling, design and characterization of a new low-jitter analog dual tuning LC-VCO PLL arehitecture[J]. IEEE Journal of Solid-state Circuits. 2005, 40 (6): 1303- 1309.
  • 8魏臻,陆阳,徐自军.数字化轨道表示模块的误差校准与检测方法研究[J].电子测量与仪器学报,2006,20(6):10-15. 被引量:1

二级参考文献4

同被引文献21

引证文献2

二级引证文献11

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部