基于FPGA的数字滤波器乘法模块改进

Improvement of The FIR Multiplication Module Based on FPGA

乘法运算是数字滤波器中的核心操作,其性能的好坏直接影响整个滤波器的特性。在数字滤波器理论及常见实现方法的基础上,介绍了能高效实现固定常系数乘法的分布式算法原理,给出了在FPGA中用查找表实现FIR滤波器的算法设计。在乘法设计模块中,根据分析结果对算法的实现进行了改进,给出了减小误差的设计方案。该设计借助仿真软件对该方案进行验证,其结果表明数字滤波器的实现方法减小了误差,其性能优于传统的数字滤波器。

The performance of digital system is determined by multiplication, This paper introduces the theories and common implementation methods of digital filter. It presents a theory of Distributed Arithmetic （DA） which could realize the muhiplication of constant coefficient efficiently, and introduces a method of FIR filter design using took up table（LUT） based on FPGA. One improvement is realized in the design of the multiplication module to reduce errors. The design is validated with the simulation software. The simulation result shows that this technique has such advantages as fewer errors. Its performance is much better than that of the conventional methods.