基于Verilog计算精度可调的整数除法器的设计

Design of Integer Divider with Adjustable Precision Based on Verilog

传统整数除法算法采用多次相减的方法来实现运算,相减的过程耗费了大量时钟脉冲,而且对运算结果的最后一位没有进行处理。针对传统的整数除法器,提出一种基于Verilog计算精度可调的整数除法器的设计方法,运用移位、循环减法和四舍五入的方法对数据进行处理,提高了处理速度和精确度。用Cadence公司的NC-Verilog仿真器对所设计的除法器进行仿真验证,结果显示该除法器达到了预期功能。

Traditional integer division algorithm used many subtraction to achieve the operation,the process by spending a lot of clock pulse,but also the results of the operation did not deal with the last one bit. Due to the traditional integer divider, an integer divider with adjustable precision based on Verilog is designed in this paper. The process velocity and precision of the divider are improved by using the methods of circulating subtracting and rounding to process data. The simulation for the divider is carried out by the NC - Verilog of the Cadence Company and the results indicate the good function.