基于LFSR优化的BIST低功耗设计

Design of low power consumption of BIST based on optimized LFSR

在BIST(内建自测试)过程中,线性反馈移位寄存器作为测试矢量生成器,为保障故障覆盖率,会产生很长的测试矢量,从而消耗了大量功耗。在分析BIST结构和功耗模型的基础上,针对test-per-scan和test-per-clock两大BIST类型,介绍了几种基于LFSR(线性反馈移位寄存器)优化的低功耗BIST测试方法,设计和改进可测性设计电路,研究合理的测试策略和测试矢量生成技术,实现测试低功耗要求。

During the BIST testing,LFSR as the TPG give very long test pattern for guaranteeing the fault coverage which due to a lot of power consumption.After analyzing the BIST structure and power loss model, the paper makes research on the algorithm and realization of lower power BIST on base of optimized LFSR aiming at two kinds of BIST architecture： the test-per-clock and test-per-scan. In order to meet testing lower power,the design methods for low power BIST circuit and reasonable test strategy are studied.