虚通道数和时钟比率对片上网络的影响

Virtual channel number effect and clock ratio effect for a network-on-chip

为了优化片上网络的性能和实现面积,基于环状和蜘蛛网状的拓扑结构和片上网络局部化自相似数据源,分析了虚通道数目和时钟比率对片上网络延迟和吞吐量性能的影响;并在可编程器件EP2S180F1508C5上实现了支持全局异步局部同步结构和虫孔交换的路由节点,分析了虚通道数目对路由节点面积的影响。仿真结果表明:在片上网络局部化自相似数据源下,为了使片上网络达到较高的吞吐量和较低的传输延迟并占用较少的硅片面积,路由节点必须设置3个虚通道和至少2¨1的时钟比率。

A cost-effective network-on-chip （NoC） design was developed by analyzing the effect of the virtual channel number and the clock ratio based on the Ring and Spidergon NoC topologies and localized self-similar distributed data sources. A router supporting a globally asynchronous locally synchronous （GALS） architecture was implemented on a programmable EP2S180F1508C5. Simulations show that with the localized self-similar distributed data source, at least 3 virtual channels and a 2：1 clock ratio are needed to get a relatively high throughput and a low average latency in a relatively small area.