摘要
利用线性“与或”门与高速ECL开关电路设计了一种JK触发器电路,并讨论了应用线性“与或”门设计超高速数字电路的准则以及有关的组合和时序电路设计实例.
By using of linear AND-OR gate and the high-speed ECL switch units circuit,a JK trigger circuit is designed.The paper discusses principle of super-high-speed digital circuits and some examples of combinational and sequential circuits using linear AND-OR gate are given.
出处
《云南大学学报(自然科学版)》
CAS
CSCD
1998年第1期37-40,共4页
Journal of Yunnan University(Natural Sciences Edition)
关键词
逻辑电路
超高速数字电路
触发器
数字集成电路
linear AND-OR gate,logic circuits,super-high-speed digital circuits,trigger