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双游程编码的无关位填充算法 被引量：6

The Algorithm of Filling X Bits in Dual-Run-Length Coding
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摘要 双游程编码是集成电路测试数据压缩的一种重要方法,可分为无关位填充和游程编码压缩两个步骤.现有文献大都着重在第二步,提出了各种不同的编码压缩算法,但是对于第一步的无关位填充算法都不够重视,损失了一定的潜在压缩率.本文首先分析了无关位填充对于测试数据压缩率的重要性,并提出了一种新颖的双游程编码的无关位填充算法,可以适用于不同的编码方法,从而得到更高的测试数据压缩率.该算法可以与多种双游程编码算法结合使用,对解码器的硬件结构和芯片实现流程没有任何的影响.在ISCAS89的基准电路的实验表明,对于主流的双游程编码算法,结合该无关位填充算法后能提高了6%-9%的测试数据压缩率. The dual-run-length codes are the important technique for test data compression. Test compression has two steps： first,the don＇ t-care bits in the test data are filled with 0 or 1s and the test data are divided into rtm sequences;second,every run in the sequences is converted to the compression code according to the given encoding algorithm. However, all the former existing papers focus on the second step, ignoring the importance of the first step thus to lose a certain potential compression ratio. In this paper, we address the importance of don＇ t-care bits filling to test data compression ratio and propose a novel algorithm, which fills don＇ t-care bits according to the selecting codes to achieve the higher compression ratio. This algorithm can be used with many dualrun-length codes without impacting on the decoder structure or the chip implementation flow. For the mainstream dual-run-length codes,the compression ratio is improved by 6%-9%.
作者 方昊 姚博 宋晓笛 程旭
机构地区 北京大学理科
出处 《电子学报》 EI CAS CSCD 北大核心 2009年第1期1-6,共6页 Acta Electronica Sinica
基金 国家863高技术研究发展计划(No.2006AA010202)
关键词 集成电路测试 测试数据压缩 游程编码 无关位填充 IC test test data compression run-length codes fill don＇ t-care bits
分类号 TP391.76 [自动化与计算机技术—计算机应用技术]
  • 相关文献

参考文献16

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二级参考文献32

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共引文献97

同被引文献86

  • 1方建平,郝跃,刘红侠,李康.应用混合游程编码的SOC测试数据压缩方法[J].电子学报,2005,33(11):1973-1977. 被引量：20
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引证文献6

二级引证文献26

电子学报
2009年 第1期

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