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一种128位高精度浮点乘加部件的研究与实现 被引量：4

Research and Realization of a 128-Bit Multiply-Add-Fused Unit
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摘要 高性能高精度的浮点数值处理一直是科学计算追求的目标。为此,本文研究并实现了一种128位浮点乘加融合计算单元。在乘法模块中,使用分块乘法,复用57位乘法模块,减小了数据宽度。采用三输入前导1预期技术,简化了预编码,缩短了预测电路的延时并减小面积。该模块单元使用Verilog语言实现,用Design Compiler进行逻辑综合,在simc0.13μm工艺下频率达202MHz,关键路径延时为4.93μs,面积约为191000门。 High-performance and high-precision floating-point processing has been the object of scientific computing. This paper propgses the design of a 128-bit fused multiply-add unit. In the multiplication module reuse of the 57bit multiplication modules, the width of the data is reduced. This enhanced multiply-add-fused unit needs a LOP circuit to deal with three operands, simplify the encoding, shorten the delay and reduce the circuit size. The synthesis result shows that the design can work at 202MHz, the data arrival time is 4. 93μs, the area is 191,000 gates.
作者 张峰 黎铁军 徐炜遐
机构地区 国防科技大学计算机学院
出处 《计算机工程与科学》 CSCD 北大核心 2009年第2期93-96,103,共5页 Computer Engineering & Science
关键词 乘加融合 三输入前导1预测 浮点部件 multiply-add-fused（MAF） 3-operand leading-one-prediction floating unit
分类号 TP332.2 [自动化与计算机技术—计算机系统结构]
  • 相关文献

参考文献10

  • 1ANSI/IEEE Std 754-1985, IEEE Standard for Binary Floating-Point Arithmetic[S].
  • 2Sun Mierosystems Inc. OpenSpareTM T1 Microaxchiteeture Specification. Part No. 919-6650-10[S].
  • 3Montoye R K, Hokenek E, Runyon S L. Design of the IBM RISC System/6000 Floating-Point Execution Unit[J]. IBM Journal of Research and Development, 1990, 34 (1), 59-70.
  • 4Gerwig G, Wetter H, Schwarz E M, et al. The IBM eServer z990 Floating-Point Unit[J]. IBM Journal of Research and Development, 2004,48(3-4):311-322.
  • 5Rabaey J M, Chandrakasan A, Nikolic B. Digital Integrated Circuits: A Design Perspective[M]. 2nd ed. 北京:清华大学出版社,2004:586-594.
  • 6Bruguera J D, Lang T. Leading-One Prediction with Concurrent Position Correction [J]. IEEE Trans on Computers, 1994,48(10) : 1083-1097.
  • 7Tomas L, Javier B D. Floating-Point Multiply-Add Fused with Reduced Latency[J]. IEEE Trans on Computers, 2004, 53(8):988-1003.
  • 8梅小露.浮点乘加部件中三操作数前导1预测算法的设计[J].微电子学与计算机,2005,22(12):16-20. 被引量：8
  • 9张峰,黎铁军,徐炜遐.一种浮点乘加部件的测试方法[C]//第十一届计算机工程与工艺学术年会论文集,2007:322-324.
  • 10凌志强.支持并行整数乘的双通路浮点融合乘加结构的研究与实现:[工学硕士学位论文][D].长沙:国防科技大学,2005.

二级参考文献5

  • 1Tomas Lang, Javier D Bruguera. Floating-Point MultiplyAdd-Fused with Reduced Latency. IEEE Transactions on Computers, 2004, 53(8): 988～1003.
  • 2Martin S Schmookler, Kevin J Nowka. Leading Zero Anticipation and Detection-A Comparison of Methods. Vail,Colorado: Proceedings of the 15th IEEE Symposium on Computer Arithmetic, 2001: 7～12.
  • 3Hokenek E, Montoye R K, Cook P W. Second-Generation RISC Floating Point with Multiply-add Fused. IEEE Journal of Solid-State Circuits, 1990, 25(5): 1207～1213.
  • 4Vojin G Oklobdzija. An Algorithmic and Novel Design of a Leading Zero Detector Circuit: Comparison with Logic Synthesis. IEEE Transactions on VLSI Systems, 1994, 2(1):124～128.
  • 5Javier D Bruguera, Tomas Lang. Leading-one Prediction with Concurrent Position Correction. IEEE Transactions on Computers, 1999,48(10): 1083～1097.

共引文献7

同被引文献35

  • 1Bailey D H. High-precision floating-point arithmetic in scientific computation [J]. Computing in Science and Engineering, 2005,7 (3) :54-61.
  • 2IEEE Computer Society. IEEE Standard for Floating-Point A- rithrnetic[S3. IEEE Standard 754-2008, 3 Park Avenue New York, NY 10016-5997, USA, August 2008.
  • 3Akkas A,Sehulte M J. Dual-Mode Floating-Point Multiplier Ar- chitectures with Parallel Operations [J]. Journal of Systems Ar- chitecture, 2006,52 : 549-562.
  • 4Akkas A. Dual-Mode Quadruple Precision Floating Point Adder [C] 9th Euromiero Conference on Digital System Desigr. 2006:211-220.
  • 5Akkas A. A Dual-Mode Quadruple Precision Floating-Point Di-vider[C] // Fortieth Asilomar Cord'erence on Signals, Systems and Computers. 2006 : 1697-1701.
  • 6Gok M, Ozbilen M M. Multi-functional floating-point MAF de- signs with dot product support [J]. Microeleetronics Journal, 2008,39 (1): 30-43.
  • 7Huang Li-bo, Ma Sheng, Shen Li, et al. Low-Cost Binary128 Floating-Point FMA Unit Design with SIMD Support[J]. IEEE Transactions on Computers,2012,61(5) :745-751.
  • 8Yu Xiao-yan, Chan Yiu-Hing, Curran B, et al. A 5GHz+ 128-bit Binary Floating-Point Adder for the POWER6 Processor[C]// Proceedings of the 32nd European Solid-State Circuits Confe- rence. 2006:166-169.
  • 9Intel Company. Intel Compilers and Libraries [EB/OL]. http:// soft-ware, intel, coaerrus/artides/intel-cimpilers/, 2012,12/24.
  • 10Fousse L, Hanrot G, Lefevre V, et al. Mpfr: A multiple-precision binary floating-point library with correct rounding [J]. ACM Transactions on Mathematical Software (TOMS), 2007,33(2) : 1-14.

引证文献4

二级引证文献5

计算机工程与科学
2009年 第2期

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