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片上网络:一种新兴的片上系统设计方法 被引量：1

Networks on Chip:A Novel SOC Design Method
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摘要 本文主要探讨了片上网络目前的发展状况和趋势,对比其他网络总结了片上网络的优缺点,并着重分析了片上网络的拓扑结构、通信方式。 This paper introductes the evolution of networks on chip, summarizes the merits and demerits of NOC, and analyses the topological configuration, and the communication mode of NOC.
作者 张浩 张盛兵
机构地区 西北工业大学计算机学院
出处 《计算机工程与科学》 CSCD 北大核心 2009年第2期97-99,共3页 Computer Engineering & Science
关键词 片上系统 片上网络 资源和路由器 服务质量 功耗 systems on chip networks on chip resources and routers QoS power
分类号 TN402 [电子电信—微电子学与固体电子学]
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参考文献10

  • 1Dally W, Poulton J. Digital Systems Engineering[M]. New York:Cambridge University Press, I998.
  • 2Benini L, de Mieheli G. Networks on Chip: A New Paradigm for Systems on Chip Design [C]//Proc of the 2002 Design, Automation and Test in Europe Conf and Exhibition, 2002.
  • 3Millberg M, Nilsson E, Thid R, et al. The Nostrum Backbone:A Communication Protocol Stack for Networks on Chip [C]//Proc of the VLSI Design Conf, 2004.
  • 4Murali S, de Micheli G, Jalabert A, et al. XpipesCompiler: A Tool for Instantiating Application Specie Networks-on- Chip[C]//Proc of Design, Automation and Test in Europe, 2004: 884-889.
  • 5Jantsch A, Tenhunen H. Networks on Chip[M]. Amsterdam: Kluwer Academic Publishers, 2003.
  • 6Goossens K, Dielissen J, Radulescu A. The Thereal Network on Chip: Concepts, Architectures, and Implementations[J]. IEEE Design and Test of Computers,2005,22(5) : 21-31.
  • 7Benini L,de Micheli G. Networks on Chips: A New SoC ParadigmJ]. IEEE Computer, 2002,35 (1) : 70-80.
  • 8Pinto A, Carkoni L P, Sangiovanni-Vincentelli A L. Effieent Synthesis of Networks on Chip[C]// Proc of the 21 st Int'l Conf on Computer Design, 2003.
  • 9Goossens K, van Meerbergen J, Peeters A, et al. Networks on Silicon: Combining Best-Eortand Guaranteed Services[C] //Proc of Design, Automation and Test in Europe Conl and Exhibition, 2002 : 423-425.
  • 10Nurmi J, Tenhunen H, Isoaho J, et al. Interconnect-Centric Design for Advanced SoC and NoC[M]. Amsterdam:Kluwer Academic Publishers, 2004.

同被引文献7

  • 1Chou Chenling, Marculescu R. User-centric Design Space Exploration for Heterogeneous Network-on-Chip Platforms[C]// Proc. of Conference on Design, Automation and Test in Europe. [S. 1.]: IEEE Press, 2009: 15-20.
  • 2Grot B, Hestness J, Keckler S W, et al. A Heterogeneous Network- on-Chip Architecture for Scalability and Service Guarantees[C]// Proc. of the 38th Annual International Symposium on Computer Architecture. [S. 1.]: ACM Press, 2011.
  • 3Ogras U Y, Marculescu R. "It's a Small World After All": NoC Performance Optimization via Long-range Link Insertion[J]. IEEE Trans. on Very Large Scale Integration Systems, 2006, 14(7): 693-706.
  • 4Guz Z, Walter I, Bolotin E, et al. Efficient Link Capacity and QoS Design for Network-on-Chip[C]//Proc. of Conference on Design, Automation and Test in Europe. [S. 1.]: IEEE Press, 2006.
  • 5Dally W, Towles B. Principles and Practices of Interconnection Networks[M]. San Francisco, USA: Morgan Kaufmann Publishers, 2003.
  • 6Dally W J. Virtual-channel Flow Control[J]. IEEE Trans. on Parallel and Distributed Systems, 1992, 3(2): 194-205.
  • 7赖明澈,王志英,郭建军,戴葵.具有拥塞缓解策略的动态虚拟通道研究及其VLSI实现[J].计算机学报,2008,31(11):2026-2037. 被引量：8

引证文献1

二级引证文献2

计算机工程与科学
2009年 第2期

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