摘要
针对ＣＭＯＳ个别电路的静态功耗电流ＩＤＤ功率老化失效问题，根据ＣＭＯＳ的设计结构和工艺特点，本文从静电和栓锁的角度提出了几种失效模型并分析了ＩＤＤ几种失效机理。
The static power current I DD power ageing lose efficiency of CMOS individual circuit is directed based on the structure and technology of the CMOS,from the point of view of electrostatic and latch up,a few lose efficiency models are presented and I DD several lose efficiency mechanism are analysed.
出处
《半导体技术》
CAS
CSCD
北大核心
1998年第2期24-28,共5页
Semiconductor Technology
关键词
静态功耗电流
失效模型
CMOS
IC
测试
Static power current Power ageing Lose efficiency model Microelectronics test pattern
