基于Verilog-A的Sigma Delta系统行为级建模

Sigma Delta Modulators Behavioral Modeling Based on Verilog-A

介绍Verilog-A设计语言的特点,基于Sigma Delta系统介绍分级设计思想。分析开关电容型Sigma Delta调制器的非理想特性,主要包括时钟抖动、开关热噪声、运放增益、摆率等。在建立各自噪声模型的基础上,基于Verilog-A对二阶Sigma Delta系统行为级完整建模,通过仿真结果的比对,验证Verilog-A建模,总结其可准确预测指标并在一定程度上有效地削减仿真时间的优点。

This paper introduces the use of Verilog-A, which provides the capability to model the circuit topology of Sigma Delta modulators closely to the electrical level and achieving a considerable reduction of simulation time. It introduces how to design Sigma Delta system by hierarchical design methodology. Non-idealities of switched-capacitor Sigma Delta modulator, such as sam- pling jitter, kT/C noise and operational amplifier noise, are analyzed. Models for these noises are established, and a second-order Sigma Delta modulator is constructed based on Verilog-A. Simulation results demonstrate the validity of these models using Verilog-A.