关于三值维持阻塞JK触发器的研究

Development of a Ternary Edge Triggered JK Flip Flop

提出了一种具有三轨输出的三值维持阻塞ＪＫ触发器电路，描述了该触发器电路的设计。对由ＴＴＬ门电路组成的试验电路进行了计算机模拟和测试。结果表明，该触发器能实现预定的功能。

A ternary edge triggered JK flip flop with a three rail output is proposed in the paper.The design of the circuit is described.An experimental circuit composed of TTL gates has been developed.Computer simulation and test on the experimental circuit show that the flip flop is capable of performing the predetermined logic functions.