摘要
本文对现有的IC制造中真实缺陷轮廓的建模方法进行了比较,得到了一些有意义的结果。该结果为进行有效的集成电路(IC)成品率预报及故障分析提供了有益的借鉴。
The approaches to model the real defect outlines in the IC manufacturing process are compared and some useful conclusions are obtained. The results obtained in this paper will be helpful for yield prediction and fault analysis of IC.
关键词
IC缺陷
IC故障
制造工艺
IC defect, Defect model, Fault-probability, Local equivalent circular defect
