基于ASIC的直接数字频率合成器前端设计与实现

Design and Implementation of Front-End of DDS Based on ASIC Flow

对基于ASIC设计流程的直接数字频率合成器(DDS)进行系统架构以及模块划分和算法分析;利用Verilog HDL进行RTL级功能仿真与测试平台的编写;完成模块中所有数字部分的设计、仿真,直至综合优化和时序分析的全过程。为满足高频率和低抖动的要求,需要反复综合,并充分考虑速度和面积等方面的影响;最后,对采用DDS实现数字调制进行了功能仿真与测试。

System architecture of a direct digital synthesizer （DDS） was constructed based on ASIC design flow. Module partitioning and algorithm analysis were described. Functional simulation at RTL level was performed and test-bench was written using Verilog HDL. All digital portions in the module were designed and simulated, and syn- thesis optimization and timing analysis were also performed. To meet the requirement of high frequency and low jitter, repeated synthesis was necessary, in which speed and area should be taken into consideration. Finally, digital modulation with DDS was functionally simulated and tested.