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一种高速自适应Reed-Solomon译码结构及其VLSI优化实现 被引量：4

An Architecture and VLSI Implementation for Adaptive Reed-Solomon Decoder
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摘要 该文给出了一种自适应Reed-Solomon(RS)译码器结构。该结构可以自适应地处理长度变化的截短码编码数据块,适合于高速译码处理。该结构使译码处理不受数据块间隙长短的约束,既可以处理独立的编码数据块也可以处理连续发送的编码数据块。另外本译码器结构可以保证输出数据块间隔信息的完整性,满足无线通信和以太网中特殊业务的要求。本文还基于该结构对RS(255,239)译码器予以实现,该译码器经过Synopsys综合工具综合并用TSMC 0.18μm CMOS工艺实现,测试结果验证了该译码器的自适应功能和译码正确性,其端口处理速率可达1.6Gb/s。 This paper proposes the architecture of an adaptive Reed-Solomon （RS） decoder. This adaptive decoder can decode shorten RS code with variable block length as well as variable message length. The proposed RS decoder is independent of the interval of codeword block. Consequently, it can work not only in a burst mode, but also in a continuous mode. Further, this decoder can provide the integrity of interval information between codeword blocks, thus satisfying the requirements of special services in wireless communication and Ethernet. The VLSI implementation of a RS （255,239） decoder is also presented, which is based on the architecture of the adaptive RS decoder. This adaptive RS decoder has been designed and implemented with TSMC 0.18 μm COMS technology. The testing results validate the function of the adaptive RS decoder. The port rate is up to 1.6Gb/s.
作者 邱昕 张浩 亓中瑞 刘壹 陈杰
机构地区 中国科学院微电子研究所
出处 《电子与信息学报》 EI CSCD 北大核心 2009年第2期484-488,共5页 Journal of Electronics & Information Technology
基金 国家自然科学基金项目(60425413)资助课题
关键词 REED-SOLOMON 译码器 自适应译码 VLSI实现 Reed-Solomon （RS） decoder Adaptive decoding VLSI implementation
分类号 TN492 [电子电信—微电子学与固体电子学]
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参考文献11

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同被引文献33

  • 1谷銮,徐贵力,王友仁.FPGA动态可重构理论及其研究进展[J].计算机测量与控制,2007,15(11):1415-1418. 被引量：48
  • 2LONE F R, PURI A, KUMAR S. Performancecomparision of Reed-Solomon code and BCH code o- ver rayleigh fading channel [J]. International Jour- nal of Copmuter Applications, 2013,71(20):23-26.
  • 3DAS A S, DAS S, BHAUMIK J. Design of RS (255,251) encoder and decoder in FPGA [J]. Inter- national Journal of Computing & Engineering, 2013,2(6) :391-395.
  • 4DAYAL P, PATIAL R K. FPGA implementation of Reed-Solomon encoder and decoder for wireless network 802.16 [J]. International Journal of Com- puter Applications (0975-8887), 2013,68(16) : 42- 45.
  • 5TIWARI B, MEHRA R. FPGA implement of RS codec for digital video broadcasting [J]. VSRD In- ternational Journal of Electival, Electionics & Com- munication Engineering, 2012,2(2) :68-77.
  • 6Reed I S,Solomon G. Polynomial codes over certain fields[J].Soc Ind Appl Math,1960,(08):300-304.
  • 7Jiabin You,Shaochuan Wu. Design and realization of reed-solomon codes based on FPGA technique[A].China:Wuhen,2011.2086-2089.
  • 8Shu Lin;Daniel J;Costello Jr.差错控制编码[M]北京:机械工业出版社,2007.
  • 9Lee H. High-speed VLSI architecture for parallel reed-solomon decoder[J].IEEE Transactions on Very Large Scale Integration Systems,2003,(02):320-323.
  • 10Couvreur A, Gaborit P, Gaut|fier-Umafia V, et al: Distinguisher-based attacks on public-key cryptosystems using Reed-Solomon codes[J]. Designs, Codes and Cryptography, 2014, 73(2): 641 666.

引证文献4

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电子与信息学报
2009年 第2期

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