一种具有堆积抑制功能的半导体辐射探测器前端ASIC电路(英文)

A Front-End ASIC for Semiconductor Radiation Detectors with Pile-up Rejection Capability

提出了一种用于半导体辐射探测器读出的CMOS前端电路,该ASIC电路包含电荷灵敏放大器、跨导-电容型脉冲成形器、峰值检测/保持电路和甄别器,后两者结合一些逻辑电路实现了抑制脉冲成形器输出波形尾缘堆积的功能。该电路采用0.5μm、双硅三铝CMOS标准工艺设计,其核心模块电荷灵敏放大器和成形器经过了流片测试。仿真和测试结果验证了该电路的功能。

A CMOS front-end ASIC for semiconductor radiation detectors is proposed. The ASIC comprises a charge sensitive amplifier （CSA）, a gm-C type shaper, a peak detect and hold circuit （PDH）, and two discriminators. The PDH and the discriminators, together with some logic circuits, provide the capability to reject trailing edge pile-up. The circuit has been designed in a 0.5 μm DPTM CMOS technology and verified by simulation. The most noise-sensitive blocks, the CSA and the shaper, have been manufactured and measured. The simulation and measurement results show that the ASIC is capable of pile-up rejection.