FPGA可测性设计研究

Research on FPGA Mensurability Design

提出了FPGA芯片CLB模块的向量级连测试、内建自测试和互连资源内建自测试等可测性设计方法,在保证测试覆盖率的同时通过优化测试程序控制测试代价增长。

This paper presents vector measurement of CLB, BIST of CLB and internet resource, which improves measurement coverage and reduces costs of measurement program.