微处理器中异步FIFO的一种优化方法

An Optimal Approach In Design Of Asynchronous FIFO Of Microprocessor

在VLSI电路设计中,一个系统包含了多个时钟域,如何在这些不同的时钟域之间传递数据成了一个重要问题;在微处理器总线接口等多时钟系统中,采用异步FIFO传递数据是一种安全高效的方法,提出了一种优化的异步FIFO设计,以异步的方式产生标志信号,根据排队论确定最优的FIFO深度,并引入门控时钟技术降低了动态功耗;与其它设计相比,电路结构简单,在面积和功耗方面得到了改善,可以广泛在嵌入式微处理器中使用。

In VLSI circuits design, a system contains multi--clock domains, passing data among the different domains became an impor- tant problem. In multi--clock systems such as bus interface of microprocessors, passing data via asynchronous FIFO is a safe and high--effi- ciency approach. An optimal approach of designing asynchronous FIFO is presented, it generated flags asynehronously, found out the opti- mal FIFO＇s depth based on queue--theory, introduced clock gating technology to reduce the dynamic power consumption. The circuit structure is simpler, the area and power consumption cost were both improved compared with other designs, it can be widely used in embed- ded microprocessors.