运用器件模拟软件验证一种GGNMOS ESD保护电路的设计方案

The Verification of a Kind of Design Proposal of GGNMOS ESD Protection Circuit with the Device Simulation Software

随着CMOS工艺技术发展到深亚微米阶段,器件沟道的有效长度小于0.25μm,器件的高集成度增进了集成电路(IC)的性能及运算速度.但随着器件尺寸的缩减,却出现了一些可靠度的问题,其中ESD(electrostatic discharge)是当今MOS集成电路中最重要的可靠性问题之一.

With the continuous development of CMOS technology in the deep sub - micron stage, the effective channel length of device is less than 0. 25 μm, and highly integrated device has enhanced integrated circuit （IC） performance and computational speed and lower per chip the manufacturing costs. However, with the reduced size of the device, there have been some reliability problems. ESD （electrostatic discharge） is one of the most important problems of the MOS Integrated Circuits in the reliability.