8位RISC_CPU可测性设计

Design for Testability of 8 RISC_CPU

本文介绍了一款RISC_CPU的可测性设计,为了提高芯片的可测性,采用了扫描设计和存储器内建自测试,这些技术的使用为该芯片提供了方便可靠的测试方案。

In order to improve testability and reduce cost of the chip .The paper introduces DFT techniques used in the design of RISC_CPU, including techniques of scan design, memory build-in-self-test, these techniques offer convenient and reliable test schemes for general-purpose RISC_CPU chip.