基于FPGA的四相移键控调制解调器的建模与设计

Modeling and designing based on FPGA for digital QPSK modulator and demodulator

针对传统的四相移键控(QPSK)的调制解调方式,提出一种基于高速硬件描述语言(VHDL)的数字式QPSK调制解调模型。这种新建模方式便于在目标芯片FPGA/CPLD上实现QPSK调制解调功能。新的QPSK调制器根据其调制模型,采用分频器和选择开关来实现;新的QPSK解调器模型引入一个特殊相位计数模块,对已调信号的进行解调。通过理论推导和系统VHDL的编程设计与时序仿真,结果表明新型QPSK调制解调器模型在理论和实用上是可行的,并且此种设计方案减小了硬件实现的复杂度,具有可移植性好、体积小、低功耗、可靠性高、方便维护和升级等优点。

For the conventional modulation and demodulation of QPSK, the new models of modulation and demodulation on digital QPSK based on VHDL are developed. The new models can made it easy to realize QPSK modulation and demodulation on a target chip of FPGA/CPLD. The select switch is used in the new QPSK modulator, and a specific phase meter counter is used to demodulate modulated signals in the new QPSK demodulator. Based on VHDL, by system designing and simulating, the results show the model is feasible both in theory and in experiment. Such design reduces the complexity of hardware, and it has the merits of good transplant, small size, low-power consumption, high reliability, and facilitated to maintain and upgrade.