摘要
提出了一种利用CPLD实现雷达并口数据的采集和存储的方案。采用单片CPLD完成了以往需要大量外围器件来完成的雷达并口数据收发及存储功能,有效地减少了印制板上功能模块的面积,减少了系统体积,提高了设计效率;同时还利用CPLD中的锁相环倍频系统时钟大大提高系统采集速度。实践证明,基于CPLD的系统设计是灵活、现实且高效的。
Using of CPLD to achieve parallel data collection and storage options in radar system is proposed. CPLD takes the place of many peripheral components,complets to send and receive the dates of radar the parallel ports,reduces the area of PCB modules and volume of the system, and improves the designing efficiency, the PLL clock multiplier system in CPLD greatly improved system collection speed. Practice proves that, based on the CPLD. system design is flexible, practical and effective.
出处
《现代电子技术》
2009年第5期84-86,共3页
Modern Electronics Technique