多路数据采集系统中FIFO的设计

Design of FIFO in Multi-channel Data Acquisition System

首先介绍了多路数据采集系统的总体设计、FIFO芯片IDT7202。然后分别分析了FIFO与CPLD、AD接口的设计方法。由16位模数转换芯片AD976完成模拟量至位数字量的转换,由ATERA公司的可编程逻辑器件EPM7256A完成对数据的缓存和传输的各种时序控制以及开关量采样时序、路数判别。采用FIFO器件作为高速A/D与DSP处理器间的数据缓冲,有效地提高了处理器的工作效率。

The design of multi- channel data acquisition system and FIFO chip IDT7202 are introduced. Then the design method of FIFO with the CPLD, A/D interface are analysed. 16 bit analog- digital conversion chip AD976 is applied to complete the analog- to digital conversion, ATERA Company＇s programmable logic device EPM7256A is adopted to complete the data cache and transfer time sequence control, and the switching of sampling time sequence and approach discriminant. Using FIFO devices as high- speed A/D time sequence and DSP proeessor＇s data buffer,the efficiency of processor is improved effectively.