高效可配置FFT处理器的VLSI设计及其应用

VLSI Design of an Efficient Reconfigurable FFT Processor and its Application

针对正交频分复用通信系统中的快速傅里叶变换(FFT)处理器的硬件实现,提出一种高效可配置的VLSI结构.在基于存储器的FFT架构基础上,采用一种双路并行处理的数据通路和一种有效的控制方案,节省了硬件面积并提高了系统运算的效率.此外,对FFT的蝶形运算单元进行了优化,使其能处理多种运算模式.基于该结构的FFT处理器已应用于DVB-T/H系统中,并在SMIC 0.18μm工艺下进行了逻辑综合、Layout以及功耗分析,等效逻辑门数为56 k,在20 MHz工作频率下功耗约为33.5 mW.与FFT结构相比,该结构有效地减少了硬件面积和功耗.

For the hardware implementation of fast Fourier transform （FFT） processor in orthogonal frequency division multiplexing （OFDM） based communication system, this paper proposes an efficient and reconfigurable VLSI architecture. Based on the memory-based architecture, a dual-path pipelined shared-memory FFT architecture and an elaborately designed control scheme are proposed which can provide high computation efficiency with less chip area. Furthermore, a reconfigurable pipelined butterfly unit is also designed for multi-mode calculation. A test chip based on the architecture has been designed and applied to DVB-T/H system. Synthesis and layout are carried out by SMIC 0.18μm standard CMOS process and its hardware scale and power dissipation is 56 k logic gate and 33.5 mW@ 20 MHz, respectively. Compared with known VLSI architecture for FFT, the proposed design reduces area and power dissipation efficiently