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一种应用于多带正交频分复用超宽带的IFFT/FFT处理器 被引量:1

A FFT/IFFT Processor for MB-OFDM UWB Applications
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摘要 针对多带正交频分复用超宽带(MB-OFDM UWB)系统,提出了一种高吞吐量、混合字长、混合基、4并行数据路径的128点IFFT/FFT处理器结构。该处理器采用具有误差补偿的改进Booth定长乘法器和CSD常量乘法器,有效地提高了精度和减少了硬件的复杂度。通过分析,本方案比混合基多路径延迟反馈(MRMDF)结构减少了49%的乘法器资源,在硬件开销相当的情况下,比双并行数据路径结构减少了30%的存储器资源和提高了33%的吞吐量,使该处理器在精度、硬件开销和速度上做了最好的折衷。在0.18 μm COMS工艺下,该处理器的最大工作频率达到300 MHz,吞吐量为1.2Gsamples/s,满足了吉比特无线个人域网络(WPAN)的要求。 This paper presents a high-throughput, hybrid word-length, mixed-radix, four-parallel data-path 128-point FFT/IFFT processor for MB-OFDM uhrawideband (UWB) systems. The proposed processor uses an error compensation method for modified booth fixed-width multipliers and canonic signed digit (CSD) multipliers, which leads to higher precision and lower hardware complexity. From analysis, it is shown that the proposed architecture can save 49% multipliers utilizations compared to MRMDF architecture, additional our proposed architecture can save 30% memory resource and be increased by 33% throughput rate compared to the two- parallel data-path architecture under the same hardware cost. So it makes the best balance of the precision, the hardware cost and the speed. Also, ours processor is designed using 0.18 um COMS process with a throughput rate of up to 1.2 Gsample/s at 300 MHz, which meets the requirements for gigabit WPAN.
机构地区 合肥工业大学
出处 《电信科学》 北大核心 2009年第2期90-95,共6页 Telecommunications Science
基金 国家自然科学基金资助项目(No.60876028和No.60633060)
关键词 多带正交频分复用 超宽带 IFFT/FFT 无线个人域网络 MB-OFDM, UWB, IFFT/FFT, WPAN
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参考文献11

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同被引文献10

  • 1A Batra, J Balakrishnan, G R Aiello, J R Foerster, A Dabak. Design of a multiband OFDM system for realistic UWB channel environments [J]. iEEE Trans. Microw. Theory Teeh., 2004-09, (9): 2123~2138.
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  • 3J Y Oh, M SLim. Fast Fourier Transform Algorithm for Low-Power and Area-Efficient Algorithm [J]. IEICE Trans. Communications, 2006, E89-B(4): 1425-1429.
  • 4Song-Nien Tang, Jui-Wei Tsai, Tsin-Yuan Chang, A 2.4-GS/s FFT Processor for OFDM-Based WPAN Applications [J]. IEEE Journal of Circuits and Systems, 2010, 57(6): 451-455.
  • 5Y W Lin, H Y Liu, C Y Lee. A 1-GS/s FFT/IFFT processor for UWB applications [J]. IEEE Journal of Solid-State Circuits, 2005, 40(8): 1726-1735.
  • 6M Shin, H Lee. A high-speed, four-parallel radix- 2 FFT processor for UWB applications [A]. in Proe. IEEE ISCAS [C]. 2008. 960-963.
  • 7H Lee, M Shin. A high-speed Low-Complexity Two-Parallel Radix- 2^4 FFT processor for UWB applications [A]. in Proe. IEEE ASSCC [C]. 2007. 284-287.
  • 8J Lee, H Lee, S I Cho, S S Choi. A High-Speed, Low-Complexity Radix- 24 FFT Processor for MB-OFDM UWB Systems [A]. IEEE Inter. Syrup. on Circuits and Systems [C].. 4719-4722.
  • 9S M Kim, J G Chung, K K Parhi. Low Error Fixed-width CSD Multiplier with Efficient Sign Extension [J]. IEEE Transactions on Circuits and Systems-II, 2003, 50(12).
  • 10刘亮,王雪静,叶凡,仁俊彦.应用于超宽带系统中的低功耗、高速FFT/IFFT处理器设计[J].通信学报,2008,29(9):40-45. 被引量:7

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