摘要
本文分析了晶振的漂移对GPS接收机的影响,从锁相环理论的角度,重点分析了采样时钟抖动对基带载波跟踪和伪码跟踪性能的影响,并给出一种环路分级降带宽的方法来消除这种影响。该方法在保证最终伪码跟踪精度的前提下,增加了跟踪环路对动态应力的容忍范围,提高了GPS接收机跟踪环路的稳定性。
The effect of Clock ,litter on the GPS receiver is summarized, and the impact on the GPS carrier loop and code loop performance is thoroughly analyzed based on the Phased-Locked Loops theory. A robust two-stage code loop bandwidth adjusting approach is proposed to eliminate the negative effect caused by the oscillator instability. Dynamic stress tolerances can be enhanced without loss of the code tracking precision by utilizing this approach. The performance of this approach is validated by the simulation.
出处
《微计算机信息》
2009年第7期161-162,184,共3页
Control & Automation
基金
基金申请人:陈杰
项目名称:高性能卫星导航芯片与移动通信芯片的集成技术
基金颁发部门:国家高技术研究发展(863)计划(2007AA12Z344)
关键词
采样时钟抖动
载波跟踪
码跟踪
动态应力
Sample Clock Jitter
Carrier Tracking
Code Tracking
Dynamic stress