π-旋转LDPC码编码器的FPGA实现与分析

FPGA implementation of encoder for π-rotation LDPC codes and its analysis

由于LDPC编码时生成矩阵往往不是稀疏的,因而编码器的设计较复杂.对一种性能优越、编码复杂度与码长成线性关系的π-旋转LDPC码进行研究,利用FPGA实现编码器的设计.分析编码器的硬件实现原理,应用MATLAB软件进行仿真研究.应用流水线处理方案构造硬件实现电路,用Verilog-HDL语言实现编码,给出Mod-elsim6.0功能仿真波形.编码仿真结果和软件计算结果相对比,除有一些逻辑延时外,功能完全相同,实现方案切实可行.

The matrix generated with LDPC encoding is usually not the sparse one, so that the design of encoder is complex. Therefore, a kind of a-rotation LDPC codes with superior performance and linearity of encoding complexity to code length was investigated and the encoder was designed on the basis of FPGA. The implementation principle of encoder＇s hardware was analyzed and the algorithm proposed was numerically simulated with software MATLAB. In addition, the pipeline processing plan was used to construct the implementing circuit of the hardware and the Verilog-HDL language was used to implement encoding, to that the simulated waveform of Modelsim6.0 function was given. It was found from the comparison between the simulation result and that of computation with software that, except the logic time-delay to some extent, the function was completely correct and the implementation scheme was feasible.