有线数字电视用CMOS锁相环及其相位噪声分析

A CMOS Phase-locked Loop for Cable DTV and Its Phase Noise Analysis

论文设计了一个满足有线数字电视接收的CMOS锁相环集成电路。针对DVB-C接收标准,细化了电荷泵锁相环的相位域模型,根据该模型推导了各模块噪声的传输函数;对锁相环各模块的噪声特性进行了分析,根据相位误差优化目标,提出了优化重点。测试结果表明,在整个电视接收带宽内根据分析结果来优化的锁相环相位误差小于3.9°。内含该锁相环的电视调谐器实现了对DVB-C64QAM数字电视信号清晰接收。

A CMOS PLL used for digital TV receiver is designed. To satisfy DVB-C reception standard, a detailed phase-domain model for charge-pump PLLs is proposed, the transfer functions of PLL blocks are derived and the noise characters of PLL blocks are analyzed. Then the loop parameters are optimized for the rms phase error requirement. The test results show that the rms phase errors of the optimized PLL are lower than 3.9° in the whole band. The tuner using this PLL can receive DVB-C 64QAM signal clearly.