期刊文献+

一种低工艺敏感度,高PSRR带隙基准源 被引量:3

A Low Process Sensitivity,High PSRR Band-gap Reference
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摘要 实现了一种高精度带隙基准源,该基准源在预调节电路中应用了电源行波减法技术,显著改善了输出电压的电源抑制比。提出了采用电流负反馈技术稳定预调节电路电流的方法,降低了带隙基准的温度特性和电源抑制比对阈值电压的敏感度。考虑晶体管阈值电压发生±20%变化的情况下,仿真得到的基准源的温度系数和电源抑制比变化分别只有0.11ppm和7dB。测试结果表明,该基准源在-20~100℃的范围内的有效温度系数为25.7ppm/℃,低频电源抑制比为-68dB。其功耗为0.5mW,采用中芯国际0.35μm5-V混合信号CMOS工艺实现,有效芯片面积为300μm×200μm。 A high-precision bandgap reference is presented in this paper. The bandgap reference uses a pre-regulator with supply ripple subtraction technique to improve its power supply rejection ratio (PSRR). The current negative feedback technique is introduced in the pre-regulator to stabilize its output current, which improves the sensitivity of temperature coefficient and PSRR to threshold variation. Considering the±20% variation of transistor threshold, the simulated variation of temperature coefficient (TC) and PSRR are 0. 11 ppm and 7 dB respectively. The measurement result shows TC of 25.7 ppm/C from -20℃ to 100℃ and the PSRR of -68 dB in low frequency are achieved. The power consumption is 0.5 mW. It is fabricated by using SMIC 0.35 um 5-V mixed-signal CMOS process with the effective area of 300 um × 200 um.
出处 《固体电子学研究与进展》 CAS CSCD 北大核心 2008年第4期602-606,共5页 Research & Progress of SSE
关键词 带隙基准源 电源行波减法电路 预调节电路 温度系数 电源抑制 band-gap reference supply ripple subtraction pre-regulator temperature coefficient PSRR
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参考文献10

  • 1Razavi Behad. Design of Analog CMOS Integrated Circuits [M]. MC-Graw Hill, 2001:309-328.
  • 2Gray Paul R, Hurst Paul J, Lewis Stephen H, et al. Analysis and Design of Analog Integrated Circuits [M]. Fourth Edition. John Wiley, 2001:317-327.
  • 3陈浩琼,高清运,秦世才.CMOS带隙电压基准的误差及其改进[J].固体电子学研究与进展,2005,25(4):531-535. 被引量:13
  • 4Leung Ka Nang, Mok Philip K T, Leung Chi Yat. A 2-V 23-μA 5.3 ppm/C curvature-compensated CMOS bandgap voltage reference[J]. IEEE J Solid-state Circuits, 2003, 38 (3):561-564.
  • 5江金光,王耀南.高精度带隙基准电压源的实现[J].Journal of Semiconductors,2004,25(7):852-857. 被引量:28
  • 6陈碧,罗岚,周帅林.一种低温漂CMOS带隙基准电压源的设计[J].电子器件,2004,27(1):79-82. 被引量:17
  • 7Hoon S K, Chen S, Maloberti, F, et al. A low noise, high power supply rejection low drop-out regulators for wireless system-on-chip application [C]. IEEE Custom Integrated Circuits Conference, 2005: 754- 757.
  • 8Gupta V, Rincon-Mora G A, Raha P. Analysis and design of monothic, high PSR, linear regulators for SOC applications[C]. IEEE SOC Conference, 2004: 311-315.
  • 9Books T, Westwisk A L. A low-power differential CMOS bandgap reference [C]. ISSCC Dig of Tec Papers, 1994: 248-249.
  • 10Giustolisi Gianluca, Palumbo Gaetano. A detailed analysis of power-supply noise attenuation in bandgap voltage referenees[J]. IEEE T Cireuits and Systems I, 2003, 50 (2): 185-197.

二级参考文献24

  • 1Blauschild R A, Tucci P A, Muller R S, and Meyer R G. A new NMOS temperature stable voltage reference[ J ]. IEEE J.solid - state sircuit. 1978, SC - 13,767 - 774.
  • 2YANNIS P. TSIVIDIS, MEMBER IEEE, AND RICHARD W. ULMER CMOS Voltage Reference.
  • 3Behzad Razavi [ M ]. Design of Analog CMOS Integrated Circuit,
  • 4Tsividis Y P,Ulmer R W.A CMOS voltage reference.IEEE J Solid-State Circuits,1978,SC-13(6):774
  • 5Kuijk K E.A precision reference voltage source.IEEE J Solid-State Circuits,1973,SC-8(3):222
  • 6Meijer G C M,Verhoeff J B.An integrated bandgap refer-ence.IEEE J Solid-State Circuits,1976,SC-11(3),403
  • 7Brokaw A P.A simple three-terminal IC bandgap reference.IEEE J Solid-State Circuits,1974,SC-9(6),388
  • 8Brugler J S.Silicon transistor biasing for linear collector current temperature dependence.IEEE J Solid-State Circuits,1967,SC-2:57
  • 9Meijer G C M,Schmale P C,Van Zalinge K.A new curvature-corrected bandgap reference.IEEE J Solid-State Circuits,1982,SC-17(6),1139
  • 10Razavi B.Design of analog CMOS integrated circuits.Mc-Graw-Hill,2000

共引文献54

同被引文献23

  • 1秦波,贾晨,陈志良,陈弘毅.1V电源非线性补偿的高温度稳定性电压带隙基准源[J].Journal of Semiconductors,2006,27(11):2035-2039. 被引量:12
  • 2张科,郭健民,孔明,李文宏.IC Implementation of a Programmable CMOS Voltage Reference[J].Journal of Semiconductors,2007,28(1):36-41. 被引量:3
  • 3Bang-Sup Song,Paul R Gray.A precision curvaturecompensated CMOS bandgap reference[J].IEEE J of Solid-state Circuit,1983,18(6):634-643.
  • 4John Michejda,Suk K Kim.A precision CMOS Bandgap reference[J].IEEE J of Solid-state circuit,1984,19(6):1014-1021.
  • 5Qadeer Abroad Khan,Debashis Dutta.A programmable CMOS bandgap voltage reference circuit using current conveyor[C].IEEE Electronics,Circuits and Systems,2003,1:8-11.
  • 6Ka Nang Leung,Philip K T Mok,Chi Yat Leung.A 2-V 23-μA 5.3-ppm/℃ curvature-compensated CMOS bandgap voltage reference[J].IEEE J of Solid-state Circuit,2002,38(3):561-564.
  • 7Malcovati P,Maloberti F,Pruzzi M,et al.Curvature compensated BiCMOS bandgap with 1 V supply voltage[C].IEEE European Solid-state Circuits Conference,2000,19:7-10.
  • 8Made Gunawan,Gerard C M Meijer,Jeroen Fonderie,et al.A curvature-corrected low-voltage Bandgap reference[J].IEEE J of Solid-state Circuit,1993,28 (6):667-670.
  • 9Behzad Razavi.Design of Analog CMOS Integrated Circuits[M].New York:McGraw-Hill,2001.
  • 10Yue Wu,Vladimir Aparin.A monolithic low phase noise 1.7 GHz CMOS VCO for zero-IF cellular CDMA receivers[C].IEEE International Solid-state Circuits Conference,2004,1:396-535.

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