摘要
用CMOS反相器作比较器设计了一个3位的高速低功率flash ADC核。该ADC核可以应用到分级型和流水线型结构的ADC中,实现更高的转换位数。该3位ADC核采用Choudhury等人提出的编码方案,解决了高速ADC的编码电路问题。采用SMIC的0.35μm/3.3CMOS工艺模型,用Candence软件进行仿真,该3位ADC速度高达2Gsps,在该速度下具有0.56mW的低功率。
A 3 - bit low - power ADC core has been designed using CMOS inverter. The 3 - bit ADC core can be used in muti - stage ADC and pipeline ADC to achieve higher resolution. In the design of the 3 - bit ADC, the encoding scheme proposed by Choudhury et al. was used to solve the problem of encodingcircuit of high -speed ADC. Simulated results using Cadence＇ s EDA software with 0.35μm/3.3 CMOS model of SMIC have shown that the speed of the 3 - bit ADC could achieve 2Gsps. At this speed, the plower consumption of the ADC was only 0.56mW.
出处
《微处理机》
2008年第6期5-8,共4页
Microprocessors
