摘要
栅电介质击穿是MOSFET器件工作中主要的失效模式之一。由击穿而引起的栅泄漏不仅是电损耗增加的问题,而且对漏电流造成很大的影响。采用最新工艺制成的超薄栅电介质,把由击穿产生的漏电流作为因击穿点的扩展而损伤的沟道电流的一部分。制作栅氧厚度为2.2nm和3.5nm、不同沟道宽度的器件,使用专门的装置给器件施加应力,用统计方法研究晶体管性能的退化。分析表明,使漏电流退化的损伤半径大约在1.4μm-1.8μm之间。
Breakdown of gate dielectric is one of the most dangerous threats for reliability of MOSFET devices in operating conditions. Not only the gate leakage resulting from breakdown is a problem for power consumption issues, but the "on" drain current can be strongly affected. In this paper, we are showing that in recent technologies, featuring ultra - thin gate dielectrics, the corruption of drain current due to breakdown can be modeled as the effect of a portion of channel being damaged by the opening of the breakdown spot. Devices featuring 2.2nm and 3.5nm thick gate oxide and various channel widths are stressed by using a specialized setup , and the degradation of transistor parameters is statistically studied. The analysis shows that the radius of the damaged region responsible for drain current degradation can be estimated between 1.4μm - 1.8 μm.
出处
《微处理机》
2008年第6期54-56,共3页
Microprocessors