基于FPGA与CPCI总线的通用时统模块设计

Design of Universal Time System Board Base on FPGA and CPCI Bus

通过分析传统时统模块的工作原理以及用户对时统模块需求的不同,提出了一种基于现场可编程门阵列(FPGA)来实现通用时统模块的设计方法,该方法基于一片FPGA芯片,其内部实现了同步脉冲的提取、对时功能、自守时、脉宽调制等功能,与以往的各种方法相比,具有可重配置、可扩展性、灵活性、通用性、功耗低的优点,同时提高了同步精度,具有较强的抗干扰性。解决了传统时统模块定时精度不高、设置固定只能满足单一需求等问题。

This paper analyses the principle of traditional client of time system and discusses the user＇s requirement.Based on field programmable gate array （FPGA）,a new method of achieving all-purpose of time system and producing periodical signal,is put forward.With one chip and compared with the format methods,the way of decoder realizing has its advantages of flexibility,opening,extending,smallness and low consuming.Meanwhile,it enhances the precision of synchronous,as well as the anti-jamming ability.