期刊文献+

2D Mesh片上网络中交换机服务性能影响的研究及其拓扑改进 被引量:5

Study of the Impact of Switch Service Performance on 2D Mesh Network on Chip And Its Improved Topology
下载PDF
导出
摘要 本文研究了交换机服务性能对2D Mesh片上网络的缓冲区资源和端到端延时的影响,发现在较低的丢包率的情况下,即使交换机能够提供很高的服务性能,却难以节省其所使用的缓冲区资源的现象.针对该现象,提出了一种基于星型子网的网状拓扑结构SSBM(Star-Subnet-Based-Mesh),在同样的网络规模以及丢包率的情况下,该种结构与2D Mesh结构相比具有更少的端到端通信延时,并且能够以较少的交换机服务性能为代价来节省较多的缓冲区资源,在较大程度上优化了2D Mesh片上网络的面积. This paper studies the impact of switch service performance on buffer resources and end-to-end delay of typical 2D Mesh Network on Chip.A phenomenon is found that buffer resources used in 2D Mesh network on chip are very difficult to be saved even if with very high switch service performance under low drop rate.A kind of Star-Subnet-Based-Mesh(SSBM) network on chip is presented according to this phenomenon With the same network scale and drop rate,SSBM shows less end-to-end delay,less buffer resources used and less chip area at the cost of a little switch service performance than 2D Mesh topology.
作者 赵宏智
出处 《电子学报》 EI CAS CSCD 北大核心 2009年第2期294-298,共5页 Acta Electronica Sinica
基金 北京交通大学人才基金(No.2007RC056)
关键词 片上网络 星型子网 二维网格结构 交换机服务性能 network on Chip star-subnet 2D mesh switch service performance
  • 相关文献

参考文献13

  • 1J Dielissen, A Radulescu, K Goossens, et al. Concepts and implementation of the Philips Network-on-Chip [R ]. IP-Based SoC Design,Philips Co. Ltd,2003.
  • 2P Gueerrier, A Greiner. A generic architecture for on-chip packet-switched interconnections[A]. Proc Int Conf on Design, Automation and Test in Europe(DATE) [ C ]. New York, USA: ACM. 2000. 250 - 256.
  • 3U Y Ogras, R Marculescu. Application specific Network-on- Chip architecture customization via long-range link insertion [A]. Proc. ICCAD[ C ]. Washington DC, USA: IEEE Computer Society, 2005.246 - 253.
  • 4S Kumar. A Network on Chip architecture and design methodology[A]. Proceedings of ISVLSI[C]. Washington, DC, USA: IEEE Computer Society,2002.117 - 124.
  • 5Moraes F, Calazans N, Mello A, et al. HERMES: an infrastructure for low area overhead packet switching Networks-on-Chip [J] .The VLSI Journal Integration (VJI) ,2004. (38):69 - 93.
  • 6Sun Y R, Kumar S, Jantsch A. Simulation and evaluation of a network on chip architecture using ns-2[ A ]. Proc of the IEEE NorChip Conference [ C ]. Copenhagen, Denmark: BlackWell. 2002.53 - 58.
  • 7L Bononi, N Concer. Simulation and analysis of network on chip architectures: ring, spidergon and 2D Mesh[A]. DATE Designers' Forum[ C]. 3001 Leuven, Belgium: European Design and Automation Association. 2006. 154 - 159.
  • 8J Hu, M Radu. Application specific buffer space allocation for Networks-on-Chip router design[A]. Proc. ICCAD[ C]. Washington DC, USA: IEEE Computer Society. 2004. 354 - 361.
  • 9Adve V S, Vernon M K. Performance analysis of mesh interconnection networks with deterministic routing[J]. IEEE Transaction on Parallel and Distributed Systems, 1994 ( 5 ) : 225 - 246.
  • 10D Kim, M Kim, Sobelman G E. CDMA-based Network-on- Chip architecture[ A]. Proc of Circuits and Systems[ C ]. Minnesota, USA: University of Minnesota 2004. 137 - 140.

二级参考文献14

  • 1Bertozzi D,Jalabert A,Srinivasan M,Tamhankar R,Stergiou S,Benini L,De Micheli G.Noc synthesis flow for customized domain specific multiprocessor systemson-chip[J].IEEE Transactions on Parallel and Distributed Systems,2005,16(2):113-129.
  • 2Lahiri K,Raghunathan A,Dey S.Design space exploration for optimizing on-chip communication architectures[J].IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2004,23(6),952-961.
  • 3Srinivasan K,Chatha K S,Konjevod G.Linearprogramming-based techniques for synthesis of network-on-chip architectures[J].IEEE Transactions on Very Large Scale Integration (VLSI) Systems,2006,14(4):407-420.
  • 4Dick R P,Rhodes D L,Wolf W.Tgff:task graphs for free[A].In Proceedings of the Sixth International Workshop on Hardware/Software Codesign[C].Los Alamitos,CA,USA:IEEE,1998,97-101.
  • 5Sherwani N A.Algorithms for VLSI Physical Design Automation[M].Norwell,Massachusetts,USA:Kluwer Academic Publishers,1993.
  • 6Hu J,Marculescu R.Energy-and performance-aware mapping for regular NoC architectures[J].IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2005,24(4):551-562.
  • 7Lahiri K,Raghunathan A,Dey S.Design space exploration for optimizing on-chip communication architectures[J].IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,,2004,23(6):952-961.
  • 8Srinivasan K,Chatha K S.ISIS:A Genetic Algorithm Based Technique for Custom On-Chip Interconnection Network Synthesis[A].In Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design (VLSID'05)[C].Washington,DC,USA:IEEE Computer Society,2005.623-628.
  • 9Murali S,Micheli G D.SUNMAP:a tool for automatic topology selection and generation for NoCs[A].In Proceedings of the 41st annual conference on Design automation[C].New York,NY,USA:ACM Press,2004.914-919.
  • 10Srinivasan K,Chatha K,Konjevod G.Linear-programming-based techniques for synthesis of network-on-chip architectures[J].IEEE Transactions on Very Large Scale Integration (VLSI) Systems,2006,14(4):407-420.

共引文献7

同被引文献82

引证文献5

二级引证文献17

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部