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新型的高层次测试综合方法

New Method of High-Level Test Synthesis
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摘要 提出了一种基于遗传算法的高层次测试综合方法.该方法在调度、模块分配和寄存器分配过程中考虑电路的可测性问题.给出了一种可以同时进行高层次调度和模块分配的遗传算法染色体编码,并设计了基于数据依赖的单点杂交算子和基于控制步约束的变异算子,避免了进化过程中不可行解的产生.实验结果表明,该方法有效地改善了可测性. A high-level test synthesis based on genetic algorithm is proposed. This can give consideration to the testability problem in process of scheduling, module allocating and register allocating. Meanwhile, a chromosome coding of genetic algorithm is proposed, which can be used for high-level scheduling and module allocating simultaneously. A one point crossover operator based on data depen- dence and a mutation operator based on control step constrain are designed to avoid the generation of infeasible solutions. The efficiency of testability improvement has been demonstrated by experiment.
作者 孙强 马光胜
出处 《北京邮电大学学报》 EI CAS CSCD 北大核心 2009年第1期34-38,共5页 Journal of Beijing University of Posts and Telecommunications
基金 国家自然科学基金项目(60273081)
关键词 高层次综合 可测性 遗传算法 high-level synthesis testability genetic algorithm
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参考文献7

  • 1Lee M T. High-level test synthesis of digital vlsi circuits [M]. Norwood: Artech House, 1997. 36-62.
  • 2Sun Qiang, Zhou Tao. A novel register allocation algorithm for testability[J]. Tsinghua Science and Technology, 2007, 12(S1). 57-60.
  • 3Safari S, Jahangir A H, Esmaeilzadeh H. A parameterized graph-based framework for high-level test synthesis [J]. Integration, the VLSI Journal, 2006, 39(4) : 363- 381.
  • 4Hermanani H, Saliba R, An evolutionary algorithm for the testable allocation problem in high-level synthesis[J]. J Circuits Syst Comput, 2005, 14(2) : 347-366.
  • 5Harmanani H, Aoun H. An incremental approach for test scheduling and synthesis using genetic algorithms [ C ]// Proceedings of the Second IEEE NEWCAS. Montreal: IEEE Press, 2004. 69-72.
  • 6Hariyama M, Aoyama T, Kameyama M. Genetic approach to minimizing energy consumption of VLSI processors using multiple supply voltages[J]. IEEE Transactions on Computers, 2005, 54(6) : 642-650.
  • 7孙强,周涛,马光胜,李海军.一种基于遗传算法的高层次测试综合方法[J].计算机工程与应用,2007,43(30):20-22. 被引量:1

二级参考文献13

  • 1Tseng C J,Siewiorek D P.Automated synthesis of data paths in digital systems[J].IEEE Trans on Computer Aided Design, 1986, CAD-5 : 379-395.
  • 2McFarland M C,Parker A C,Camposano R.The high-level synthesis of digital systems[C]//Proceedings of IEEE, 1990:301-317.
  • 3Jaewon S,Taewhan K,Preeti R P.An integrated algorithm for memory allocation and assignmentin high-level synthesis[C]//Proceedings of the 39th Conference on Design Automation.New York:ACM Press, 2002: 608-611.
  • 4Harmanani H,Aouni H.An incremental approach for test scheduling and synthesis using genetic algorithms[C]//Proceedings of the Second IEEE NEWCAS,Montreal,June 2004:69-72.
  • 5Hermanani H,Saliba R.An evolutionary algorithm for the testable allocation problem in high-level synthesis[J].J Circuits Syst Comput, 2005, 14 (2) : 347-366.
  • 6Wafner K D,Dey S.High-level synthesis testability:a survey and perspective[C]//Proceeding of Design Automation Conference, 1996: 131-136.
  • 7Sait SA SM,Benten M S T.GSA:scheduling and allocation using genetic algorithm[C]//Proceeding of EURO-DAC94,1994:84-89.
  • 8Torbey E,Knight J.High-level synthesis of digital circuits using genetic algorithms[C]//Proc of the IEEE Conference on Evolutionary Computation, 1998.
  • 9Dhodhi M,Hielscher F.Datapath synthesis using a problem space genetic algorithm[J].IEEE Trans ICCAD,1995,14:934.
  • 10Cheng K T,Agrawal V D.A partial scan method for sequential circuit with feedback[J].IEEE Trans on Computers, 1990,39(4): 544-548.

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