H.264/AVC运动补偿的高效插值结构设计

Efficient interpolation architecture design for motion compensation in H.264/AVC

为了减少视频编解码标准H.264/AVC中运动补偿模块插值结构的硬件复杂度,提出了一种高效插值结构,包括"串行输入并行输出"亮度插值结构和只需要2个乘法器和1个加法器的色度插值结构.该插值结构采用串行输入的维纳滤波器来产生水平半像素点中间值;通过分析1/4像素插值的数据相关性来选取整像素点,优化1/4像素的滤波算法;通过分析插值窗口的重叠情况,采用垂直优先插值顺序;并且根据插值的分数像素点的不同读取不同大小的插值窗口.试验结果表明,与现有其他设计相比,该结构可以节省水平方向的6抽头FIR滤波器,减少了寄存器阵列的大小,并且节省了数据读取带宽.在H.264解码器上实现了该插值结构,仿真和综合后的结果表明,与其他设计相比,该结构的硬件复杂度更低.

For decreasing the hardware complexity of motion compensation in the video coding/decoding standard H. 264/AVC, an efficient interpolation architecture was proposed, which including a ＂serial input parallel output＂ architecture for luma interpolation and a chroma interpolation architecture which only needs two multipliers and one adder. The interpolation architecture uses serial Wiener filter for half horizontal samples, selects integer samples by analyzing the data correlation of bilinear sample filter, optimizes the quarter sample filtering, adopts vertical-first interpolation order by analyzing the overlapped region of interpolation windows, and loads small interpolation window according to the motion vector. The simulation shows that the proposed design saves the horizontal 6-tap FIR filters, reduces the size of register array, and saves the memory bandwidth. The proposed design was implemented with 0. 18 /,m CMOS technology and embedded into a H. 264/AVC decoder. Simulation and synthesis show that compared with other designs, this design has lower hardware cost.