基于循环矩阵的低密度校验码的VLSI译码设计

VLSI decoding design of low-density parity-check codes based on circulant matrices

为了解决低密度校验码(LDPC)的VLSI译码实现资源耗费庞大、功耗大、连线复杂等问题,提出了一种适用于基于循环移位单位矩阵的LDPC的结构化存储方式及相应的部分并行译码实现方法.通过分析基于循环移位单位矩阵的LDPC校验矩阵的构成方式,总结出其校验矩阵中比特节点与校验节点之间信息的传递特点,提出了一种具有高度灵活性和高效性的结构化存储方式.基于这种结构化存储方式,对迭代译码的关键步骤给出了一种部分并行的流水线时序实现方式,达到了显著降低时延和功耗的目的.最后,以中国地面数字电视广播传输标准中的LDPC码在FPGA平台上的实现为例,给出了译码性能和具体的硬件实现资源.仿真结果表明,采用该实现方法的LDPC定点译码设计在AWGN信道下得到了良好的性能,与全精度浮点实现方法相比性能差异可以忽略.

In order to resolve the problems of large area, complicated routing and high power in decoding low-density parity-check codes （LDPC）, this work presented a LDPC decoding approach, which is specified with parity check matrices based on circulant matrices, with structured memory and a corresponding partial parallel decoding architecture. By studying the structured parity matrix, the characteristic of the message passing between bit nodes and check nodes was indicated, and then a predetermined scheme of message storing with high flexibility and efficiency was proposed. Based on this scheme, a partial parallel decoding architecture was provided which significantly reduced the power and critical paths. Simulation of the LDPC in Chinese digital terrestrial television broadcasting standard on FPGA platform showed that the proposed decoding approach over AWGN channel achieved good performance, and suffered negligible performance loss compared with the. double precision while effectively reducing the operation complexity.