一种SET的SPICE宏模型及SET／CMOS混合系统仿真研究

A SPICE Macromodel and Simulation Research on the SET/CMOS Hybrid System

基于单电子晶体管(SET)数学分析模型,改进了它的SPICE宏模型.该模型考虑了背景电荷的影响,由1个电压控制电流源、1个电压控制电压源构成.与准分析模型相比较,该模型准确地表现了SET的I-U特性.通过A/D转换器的仿真实例表明,所设计的3位SET/CMOS混合系统具有良好的适用性和精确度,可以推广到SET/CMOS混合系统的管子级设计.

Based on the analytical model of single-electron transistor（SET）, its SPICE macromodel is improved. The model consists of a voltage-controlled current source and a voltage-controlled voltage source, and the effects of background charges are also considered in this model. Compared with quasi-analytical SET model, the I--U characteristics of SET can be shown more accurately using this proposed model. The results of A/D converter examples show that the designed 3-bit SET/CMOS hybrid system is an accurate and practical circuit, which can be further applied to the level design of transistors.