基于FPGA的8051IP核的设计与实现

Design and Implementation of 8051 IP Core Based on FPGA

裁减并完善了与MCS-51系列微处理器指令集完全兼容的8051IP核,减少了设计面积,提高了处理速度。按照自顶而下的设计原则,分别设计了算术逻辑单元、中心控制器、定时/计数器、串行口、RAM和ROM单元。设计采用VHDL语言进行描述并且用ModelsimSE6.0进行功能和时序验证。将8051IP核下载到Xilinx公司的FPGA(XC3S500E-4FG320C)上进行物理验证,测试了一个LED流水灯程序,结果表明软核达到预期的效果。本设计作为可移植的IP核,可以组成片上系统,用于嵌入式系统领域。

Designed and reduced 8051 IP core compatible with industrial standard MCS-51 microprocessor, not only cut down the area but also increased the processing speed.Some important units such as ALU, central controller ,timer/counter, the serial port ,RAM and ROM were designed by using Top-Down designing principle. The dasign was described by VHDL language, and verified with Model-simSE6.0 simulator. Finally, the core was downloaded into Xilinx FPGA chip（XC3S500E-4FG320C） to make physical test. The led shinning experiment was done, and the result shows that the core achieves the expected goal. The 8051 CPU core is an important part of SOPC, which can be used in many embedded domains, such as control and communication.